1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a smart power device and a method for fabricating the same, in which impact ionization to a drain region is reduced for securing a wide SOA (Safe Operation Area) and improving current driving characteristics.
2. Background of the Related Art
A power MOSFET generally has excellent switching speed, a low ON resistance and can have a low breakdown voltage of 300V and below in comparison to other semiconductor devices, which makes a high voltage lateral power MOSFET useful as a high power device for high device packing density applications. Other high power devices include DMOSFET (Double-diffused MOSFET), IGBT (Insulated Gate Bipolar Transistor), EDMOSFET (Extended Drain MOSFET), LDMOSFET (Lateral Double-Diffused MOSFET), and the like. The LDMOSFET has a variety of applications to circuits, such as an HSD (High Side Driver), an LSD (Low Side Driver) or an H-Bridge, and can be easily fabricated. However, it has disadvantages in that a threshold voltage is high due to a non-uniform doping concentration in a channel region of the LDMOSFET itself and breakdown occurs at a surface of a silicon substrate in a drift region in the vicinity of the channel. The EDMOSFET is a high voltage transistor developed recently to deal with those problems.
A related art smart power device will be explained with reference to the attached drawings. FIG. 1 illustrates a section of a related art EDMOSFET, and FIG. 2 illustrates a simulation graph showing an electric field distribution and an impact ionization occurrence extent of the related art EDMOSFET.
Referring to FIG. 1, the related art N channel EDMOSFET is provided with an n type drift region 2 (formed by one instance of ion injection) formed in a p type semiconductor substrate 1, a p type Dwell (or deep well) region 3 formed in the p-type substrate adjoining the n type drift region 2, a source region 5 and a body contact heavily doped p type impurity region 6 formed in the p type Dwell region 3, a drain region 4 formed in the n type drift region 2, insulating layers 11 formed on the surface of the substrate 1, a gate electrode 7 formed in one of the insulating layers 11, a field plate 8 formed adjacent to (and aligning with) one side edge of the gate electrode 7 and over the n type drift region 2, source electrode 10 and a drain electrode 9 in contact with the source region 5 and the drain region 4, respectively.
The gate electrode 7 is formed such that the one side edge thereof is positioned at an interface of the n type drift region 2 and the p type Dwell region 3. The source region 5 and the drain region 4 are formed by doping with n type impurities, heavily, i.e., both are n+ type. The field plate 8 is formed over the one side edge of the gate electrode 7 and the n-type drift region 2 in a metal wiring formation. The field plate 8 disperses an electric field formed in the n type drift region 2 during operation, to obtain a higher breakdown voltage.
In the aforementioned related art smart power device, upon application of a voltage higher than Vt, which can form a channel to the gate electrode 7, an inversion layer is formed in the p type Dwell region 3. And, upon application of an operation voltage to the drain electrode 9, the n type drift region 2 is brought into a saturated depletion state, allowing electrons to move to the drain region 4. Thus, while the EDMOSFET is operative as a power device, the gate electrode 7 and the field plate 8 are brought into an equipotential state, causing the depletion region in the n type drift region 2 that disperses an electric field concentrated on an edge portion of the gate electrode 7, preventing an occurrence of breakdown at the edge portion of the gate electrode 7. And, the heavily doped p type impurity region 6 formed for use as a body contact sustains a ground voltage of the semiconductor substrate 1 through a body contact. The requirement for a high BV (breakdown voltage) performance for being operative as a smart power device can be met by an appropriate adjustment of the ion implantation dose to the n type drift region 2 and the resulting uniform distribution of an electric field utilizing a depletion region formed in the n type drift region 2 according to that dose.
FIGS. 2A and 2B illustrate three dimensional graphics of an electric field distribution and amount and position of impact ionization that occurs while the EDMOSFET is operative as a power device. It is known from the electric field distribution and amount and position of impact ionization occurrence at a gate voltage VG=9V and a drain voltage VD=75V that an impact ionization which heavily affects a secondary breakdown voltage occurs at a drain edge portion where the electric distribution is intense. That is, FIGS. 2A and 2B show that there is enough of an impact ionization to cause the secondary breakdown to occur at the drain edge portion.
The aforementioned related art smart power device causes the following problems during device operation due to existence of a parasitic bipolar transistor inside of the smart power device.
Upon application of a voltage to the drain, an electron-hole pair is formed by an impact ionization from the electric field at the drain edge. This causes an Ihole current to flow, which turns on a parasitic bipolar transistor that causes the secondary breakdown if there is a voltage difference greater than 0.7V between the p type Dwell region and the n-type drift region. The secondary breakdown, that occurs because there is no reduction of the impact ionization to the drain region, causes a problem of unstable device operation due to there being no adequate SOA (Safe Operation Area).
Accordingly, the present invention is directed to a smart power device and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a smart power device and a method for fabricating the same, which can reduce an impact ionization to a drain region thereby securing an adequate SOA (Safe Operation Area) and improving current driving performance.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
The invention, in part, provides a smart power device comprising: a second conduction type drift region formed in a first conduction type well region by having first, second and third impurity regions corresponding to first, second, and third ion injections with first, second, and third ion injection energies and first, second, and third doses; a first conduction type Dwell region formed adjoining to the second conduction type drift region; a source region and a body contact region both formed in the first conductive type Dwell region; a drain region formed in the second conduction type drift region; an insulating structure formed on an entire surface; a gate electrode layer formed in the insulating structure; a field plate formed to one side of the gate electrode layer and over the second conduction type drift region; and a source electrode layer and a drain electrode layer in contact with the source region and the drain region, respectively.
The invention also, in part, provides a method for fabricating a smart power device card, the method comprising: (a) forming a second conduction type drift region by, (a1) implanting a first does of second conductivity type impurity ions having a first energy into a first conduction type well region in a surface of the semiconductor substrate, to form a first ion injection region, (a2) implanting a second dose of second conductivity type impurity ions having a second energy into the first conduction type well region, to form a second ion injection region therein adjacent to the first ion injection region, and (a3) implanting a third dose of second conductivity type impurity ions having a third energy into the first conduction type well region, to form a third ion injection region adjacent to the second ion injection region; (b) forming a first conduction type Dwell region of a first conduction type in the semiconductor substrate adjoining the second conduction type drift region having the first, second and third ion injection regions; (c) forming a gate electrode layer such that a first side aligns with an interface between the second conduction type drift region and the first conduction type Dwell region; (d) implanting second conduction type impurity ions into the first conduction type Dwell region on a second side of the gate electrode layer and into the second conduction type drift region, to form a source region and a drain region, respectively; (e) implanting first conduction type impurity ions into a portion of the Dwell region adjacent to the source region to form a body contact region; and (f) forming a field plate adjacent over the first side of the gate electrode layer and over the second conduction type drift region.